1. Field of Invention
The present invention relates to a semiconductor manufacturing process. More particularly, the present invention relates to a damascene process.
2. Description of Related Art
With the progress of integration of semiconductor devices, the use of multi-metal interconnects are becoming wide spread. Usually, the lower the resistance of the metal layer of the multi-metal interconnects is, the higher the reliability of elements is, and the better the performance of the element can be. Among metal materials, the copper is suitable to be used for the multi-level interconnects because the resistance of copper is low. However, as it is difficult to pattern the copper in the conventional photolithographic etching technique, a dual damascene process has been developed.
The dual damascene process is a technique that involves forming a trench and a via opening in a dielectric layer and then refilling a metal to form a metal wire and a via. Typically, several material layers such as the liner layer, the dielectric layer and the metal hard mask layer are sequentially formed over the substrate having the patterned conductive layer thereon and then a portion of the dielectric layer is removed to form the dual damascene opening, exposing the patterned conductive layer, in the dielectric layer. However, the stress variation and unbalanced stress between the metal hard mask layer, the dielectric layer and the liner layer lead to the unexpected shrinking or distortion of the dual damascene opening after it has been formed. Thus, the critical dimension of the dual damascene is smaller than expected. On the other words, the dual damascene formed with the use of the metal hard mask layer would confront the problem of the line distortion, which leads to the difficulty of performing the metal refilling process. Furthermore, the structure of the dual damascene will have the defects of via open or high resistance.